Implementation of High Level Synthesis for Adaptive FIR Filtering on Embedded System

This paper presents the development of high level synthesis tools for finite impulse response (FIR) filtering application on the embedded system. A hardware description language (HDL) is used to describe the structure and behaviour of the electronic circuits and digital logic circuits. The HDL coder is a high level synthesis tool that converts the C/C++ files into.ngc files and then to generate bitstream. MATLAB is supported with Vivado in order to generate the MATLAB programming on FPGA board. Based on the least mean square (LMS) algorithm, FIR filter is developed by MATLAB generated with the HDL coder and compatible with FPGA hardware. Then, the developed algorithm is implemented and automated the verification of HDL code on Xilinx Zedboard for FIR filtering and planning including with the cost estimation and hardware usage. Simulation implementation show that the experimental results of adaptive LMS-FIR from MATLAB and Vivado can perform well for system identification.