Ramp ADC Speed-up Techniques for CMOS Image Sensors with New Image Quality Metric

Ramp analog-to-digital converters (ADC) used in column parallel complementary metal oxide semiconductors (CMOS) image sensors (CIS) trade conversion speed with size, power, and complexity to achieve optimal performance. Single slope look-ahead ramp (SSLAR) ADC was introduced to solve the speed problem of ramp ADCs used in CIS trading image quality. An enhancement technique for SSLAR speed is introduced in this paper. It uses accelerated ramp based on shot noise limitations to replace SSLAR linear ramp generator for better speed performance and image quality. Moreover, a new image quality metric is proposed to be used as a reference of performance comparison of different CIS ADCs. This metric called conversion complexity metric (CCM). Accelerated SSLAR ADC technique (A-SSLAR) provides speed improvement up to average of two times (2x) of SSLAR for same CCM and threshold.