Multi-Threaded control of NAND Flash memory array

Flash memory devices operations like read, program and erase are performed by sequences called “algorithms”. An algorithm is mainly composed of phases where accurate voltages are computed and applied to the array cells and phases where data are moved through different latches in data buffers. The fast-increasing complexity of multi-bit NAND memory algorithms made it natural to realize control logic on a microprocessor, in the form of firmware routines. The HW/FW co-design enables a safer complexity management, allows development of algorithms in parallel with physical design and allows acceleration of development time to fit aggressive time-to-market requirements. Again, to follow the increasingly performance requirements different kind of multi-thread microprocessor solutions have been proposed in the years to get the best performance-power-area (PPA) trade-off. This article proposes one possible approach to performance optimization by a multi-threaded approach, without an immediate downside for area and power. The most innovative point of the new architecture is the deep adherence between intrinsic parallelizable physical processes inside a NAND Flash and the number of threads, busses and physical executors. As shown, this solution introduces tangible advantages in terms of performance.