A low power test vector seed generation algorithm for SoC

With the rapid development of system integration and processing technology, especially the emergence of system chip, integrated circuit has entered a new period of development. As the increasing scale of SOC integration and the limited number of pins, it is necessary to build testability design logic to improve its controllability and observability. However, it will lead to the problem of high test power consumption, which will cause great harm to the circuit under test. In this paper, a new test vector seed generation algorithm is proposed. Based on the traditional LFSR reseeding technology, we introduce the low-power test vector reordering algorithm into the test vector coding technology. Because of the different order of the coded test vector seeds applied to the circuit under test, the number of hops in the circuit under test is reduced, and the goal of low-power test is achieved. In order to verify the effectiveness of the proposed scheme for power reduction, we apply it to ISCAS85 partial reference circuit, and the average power consumption reduction is 25.16%. The experimental results show that the algorithm has a good effect on reducing test power consumption.