Measurements and Simulation of Self-Heating in 40 nm SOI MOSFETs

To understand self-heating in SOI CMOS, conventional and trap-rich substrates are used to fabricate 40nm gate length NFET pairs that share the same active region. One NFET serves as a heater, while the other is used as a calibrated thermometer. Measurements of the local heating confirm the simulated temperature distribution. Heat flow out of the metal contacts reduces the self-heating in NFETs on trap-rich substrates which have reduced thermal conductivity compared to conventional SOI wafers.