Multi-Physics Evaluation of Silicon Steep-Slope Cold Source FET

With novel energy-filtering switching mechanism enabled by broken-gap-like source engineering, steep slope and high on-state current can be obtained in cold source FET (CSFET). In order to account for the energy-filtering mechanism, effective cold carrier distribution model is developed for drift-diffusion (DD) method and equivalent charge correction term is incorporated into industry standard BSIM-CMG model. We present a Si nanowire (NW) CSFET as a potential candidate for advanced technology node. Steep SS approaching 31/27 mV/dec and high I
_on
of 413/322 μA/μm are achieved in n-type and p-type CSFET at V
_DD
0.65 V, respectively. A 6T CSFET hybrid SRAM circuit shows great improvement in static noise margin (SNM) design window.