A High Dynamic Range Capacitance-to-Digital Converter with Adaptive Parasitic Compensation

This work presents a novel capacitance-to-digital converter with adaptive parasitic compensation. It realizes wide measured range and high resolution with compensation, oversampling and noise shaping techniques. The circuit is fabricated in
$0.18-\mu \mathrm{m}$
CMOS process. In the post-layout simulation, it consumes
$801\mu \mathrm{W}$
under 3V supply with 1kHz of sample frequency. This design can detect 125pF by 0.1fF of precision, which prove it to be a good candidate for high dynamic range CDC.