Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and Beyond

A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.