Optimal Utilization of Hardware for the Real Valued FFT Architectures

Real-valued Serial Commutator (RSC) FFT achieves 100 percent utilization of hardware using the irreversible logic gates for the adder/subtractor operation in the butterfly structure. These irreversible logic gates are inept in low power VLSI design. In this paper the proposed system uses the reversible logic gates for the operation. This yields in reduction of power consumption and chip area. The proposed system consumes 20 percent less power and requires 17 percent less area than the existing system.