Novel Parity Generator and Detector Design using Quantum Dots

At the beginning of the era of fabrication of the digital logic circuits using Complementary Metal Oxide Semiconductors it was well predicted by Moore that every 24 months the transistor density doubles on the same sized fabricated chip. But now what we see that we have reached a particular stage where if we further increase the transistor density, we have to integrate transistors at atomic sizes which possess a big challenge in front of us as we now have to consider the effects of the quantum tunnelling phenomenon. Hence, due to these limitations, Moore's law is now being violated. One of the applications of Quantum Physics which is called Quantum Dot Cellular Automata (also referred to as QCA) is now used to implement digital circuits. Using this technique, the information is tunnelled from one end to another without the actual flow of current thus having low power consumption and extremely small size of the order of nm. This technique is different from any previously developed technique as it uses the help of quantum tunnelling of electrons from one cell to another for the transfer of information. Also setting it apart from any conventional fabrication technique is its high-frequency operation of the order of THz and no short channel effect. The above-mentioned features make it one of the best contenders for the advanced future computing device fabrication processes. In this research paper we have designed a 2-input parity generator and 4-input parity detector and then scaled them realize practical purpose 8 bit and 16-bit communication parity generator and checker. We have reported the simulated results to be on average 20-25% efficient and better from any previously designed circuit.