FPGA deployment of neuroevolved Binary Neural Networks

Deep Learning has reached a prominent area of research thanks to advances in semiconductor technologies, with Deep Neural Network (DNN) as the pivot of change. It is capable of solving complex multi-dimensional problems. This paper focuses on one particular example, the Binary Neural Network (BNN): it uses fixed-length bits in its connections and logic functions to perform excitation operations, reducing memory requirements. The conventional use of Field Programmable Gate Arrays (FPGAs) dictates inference only of deep learning networks. This publication demonstrates how the algorithm Binary Spectrum-diverse Unified Neuroevolution Architecture (BiSUNA) can perform training and inference on FPGA by dismissing gradient descent, solving reinforcement learning and reaching maximum parallelism and energy efficiency, up to 16% faster compared to a CPU. Source code can be found in github.com/rval735/bisunaU50.