A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs

The importance of energy efficiency in compute is growing with the exponential increase in the computing requirement. Improved performance at lower power is essential to reduce energy footprint, improve battery life, and push the performance of CPUs even higher through better thermal management. The reduction of dynamic power without any impact on the maximum frequency of operation processors will have a significant role in improving energy efficiency. This paper presents an efficient timing aware connectivity optimisation technique on stdcell, which helps in reducing the dynamic power of designs by optimally connecting the input signals to the standard cell input pins. An efficient algorithm is also proposed to make the right design choices during connectivity optimisation, based on timing and power. Experiments carried out on high-performance CPU core designs, at Intel's 14nm Finfet technology, show up to 2% reduction in dynamic power, without having any impact on total negative margin, worst negative margin, output slews, and cumulative margin histogram. The ease of implementation, minimal ECO effort and less than an hour run time makes this method an easy choice, even at the late stages of design closure.