I. Introduction
Soft-errors for a sequential circuit can be divided into latch soft-errors (referred to as latch errors) and logic soft-errors (referred to as logic errors). Latch errors and logic errors are a strong function of schematic design, supply voltage, and linear energy transfer (LET) values of incident particles [1]–[3]. Logic errors additionally show a linear dependence on operating frequency and have been shown to be a cause for concern for designs requiring high frequency operations [3], [4]. This temporal dependency makes estimation of logic soft-error rates very difficult. Additionally, researchers have shown that at the 40-nm node, logic errors may dominate latch errors for circuits operating in the 1–2 GHz range of frequencies [3]. At the 7-nm node, circuits are expected to operate at frequencies upwards of 3 GHz, significantly increasing the contribution of logic errors to overall soft-error rate. As a result, it is important to characterize logic errors at advanced technologies so that accurate models for failure rates are developed. Currently available models for estimating logic errors are cumbersome and require difficult-to-obtain single-event transient pulse widths. Designers need quick estimation of logic and latch error rates during the design phase to optimize performance. Novel approaches for estimating logic errors are needed, especially those that can be easily incorporated into the design flow. This paper presents an empirical technique for estimating logic soft errors using conventional D flip flop (D-FF) shift registers.