Implementation of 128-bit Radix-4 Booth Multiplier

A description of the multiplication of two binary numbers of size 128-bits each using Radix-4 Booth's Algorithm is presented in this paper. Booth Encoder circuit, Partial Product Generator tree, and Carry save adders are the main building blocks of any Booth Multiplier. Carry Save Adder is useful for adding all the partial products that are obtained. The radix-4 Booth algorithm is used to decrease the partial products which are generated intermediately. Higher representation radix results in smaller amounts of digits for a number to be represented. Radix-4 algorithm of booth helps to reduce the partial products when compared to Radix-2 booth's algorithm by a factor of half. Radix- 4 booth's algorithm is recommended because most of the parameters performances such as delay, area and power are more efficient for the radix-4 algorithm when compared to the higher radices (like radix-8's booth's algorithm or radix-16 booth's algorithm). Partial products are minimized by using the radix-4 algorithm, as a result, the area is reduced to very minimum value. The smaller area obtained implies that the boothmultiplier used is more effective in terms of area, that implies, the delay is smaller. Speed of the multiplier is higher if delay is smaller. Simulation analysis prove that proposed radix-4 multiplier based designs are more efficient if the multiplier is 64 & 128 bits. The proposed design of radix-4 128-bit Booth Multiplier is implemented using Xilinx Vivado software.

I. Introduction

Multiplication is the fundamental operations needed in many systems of digital signal processing to generate a lot of complex operations. Multipliers, however, consume a widechip area and take a long processing period. High-speed multiplier architecture is therefore needed to enhance device computational efficiency [1]. In the arithmetic units of microprocessors, multi-media, and optical signal processors, digital multipliers are commonly used. To construct multipliers of high-speed and low power, many algorithms and designs have been proposed. In microchip implanted structure plan, binary multipliers are commonly used structure block feature, and are therefore a significant execution enhancement target: 1)

Re-coding digits of the multiplier.

2)

Digit increase of each digit by a multiplicand.

3)

By using methods of multi operand addition, the partial product cluster is reduced to two operands and

4)

Express the two operands spread expansion to achieve the ultimate result.