FPGA Implementation of DHT Through Parallel and Pipeline Structure

A discrete Hartley transform (DHT) is a transform of discrete, periodic data similar to the discrete Fourier transform (DFT). This paper focuses on FPGA implementation of Discrete Hartley Transform for a sequence of length N, such that N=4
^r
where . A proposed structure of DHT algorithm is designed in parallel as well as pipelined fashion using Verilog Hardware Description Language (VHDL). ZedBoard Zynq Evaluation and Development Kit was used to implement the same, and it was found that pipeline structure shows drastic improvement in terms of hardware utilization, power consumption and computation time (latency) required as compared to parallel structure.