Design and Analysis of a Multi-Parameter Discrete Chaotic Map Using Only Three SOI Four-Gate Transistors

In this paper, a novel chaotic map is introduced using two n-channel and one p-channel silicon-on-insulator (SOI) four-gate transistor (G
⁴
FET). The multi-gate structure of G
⁴
FET is leveraged to obtain four independent bifurcation parameters in the chaotic map with a simple three-transistor design. The four parameters are the top-gate voltage and junction-gate voltage of p-channel G
⁴
FET, and two junction-gate voltages of two n-channel G
⁴
FETs. A chaotic oscillator design is proposed using this discrete-time chaotic map circuit. The chaotic behaviour is evaluated using bifurcation diagram, Lyapunov exponent (LE), and correlation coefficient. The application of this multi-parameter chaotic oscillator is presented in a chaos-based reconfigurable logic gate. It is demonstrated that, the availability of multiple bifurcation parameters result in a significant improvement in functionality space.