Background Calibration in Pipelined SAR ADCs Exploiting PVT-Tracking Metastability Detector

A dither-based digital background calibration exploiting metastability detector (MD) to correct capacitor mismatch error and gain error in pipelined successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. The comparator resolving time is utilized for dither injection only when the residue is in the vicinity of the comparator threshold, thereby minimizing the loss of dynamic range. Besides, the residue amplifier is reused as a delay reference to construct the MD. By executing a dedicated delay- control calibration, the MD realizes a robustness against process, voltage, and temperature (PVT) variations. In addition, this paper also introduces the circuit design of the PVT-tracking MD. The schematic-based simulation results show that the delay- control calibration converges within thousands of decision cycles. The proposed bit-weight calibration is verified in a 14-bit pipelined SAR ADC. Behavioral simulation results show that, with calibration, the signal to noise and distortion ratio (SNDR) is improved from 58.2 to 79.1 dB and spurious-free dynamic range (SFDR) is increased from 64.5 to 97.1 dB.