A New PRNG Hardware Architecture Based on an Exponential Chaotic Map

Recent works have been claiming efficient hardware architectures, showing a considerable endeavor to implement chaotic maps in the digital domain. However, there is a critical issue with the chaotic degradation in the digital environment due to its finite numeric precision, that it is still an unsettled topic in the research community. Additionally, less attention has been given to synthesize a methodological approach to how to calculate the exponential function in hardware. In this paper, two novel hardware designs to represent the exponential chaotic map have been suggested. We have employed a perturbation method to avoid the chaotic degradation. 64-bit fixed-point and 32-bit floating-point formats were investigated. Moreover, an approximation of Euler's number by a finite series and the Horner's method have been undertaken to further minimize the proposed hardware. Results show that both proposed hardware architectures consume a fewer number of components. The designed systems present a positive Lyapunov exponent, which suggests a chaotic behavior. Ultimately, the NIST SP 800-22 test, the histogram, and the autocorrelation function show that the new hardware architectures present pseudo-random properties.