A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs

This paper presents a sampling speed-enhancement technique for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove this technique. The post-layout simulated SAR ADC consumes only 6.71/iW and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fj/convertion-step. Simulation results show the proposed speed-enhancement technique improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.