Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs

This paper presents dynamic switching sequence (DSS) for current-steering digital-to-analog converters (DACs). Unlike conventional static switching sequence (SSS), the proposed DSS dynamically selects from pre-defined switching sequences, and achieves a minimized integral nonlinearity (INL) that is even lower than the lower bound of traditional SSS. Moreover, it works effectively with the digital pre-distortion (DPD) technique to further reduce the residual nonlinearity. Simulation results of a 16-bit segmented DAC show an average INL reduction from 37.9 LSBs (SSS, with 17.7 LSBs as the lower bound) and 10.3 LSBs (SSS+DPD, normalized), to 8.2 LSBs (with DSS) and 0.2 LSBs (DSS+DPD).