A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique

This paper presents a 10-b 500MS/s successiveapproximation-register (SAR) analog-to-digital converter (ADC) designed using a 40nm CMOS process. The first 6-bit coarse conversion is completed by a high speed loop-unrolled architecture, while the succeeding 5 bits are obtained by a traditional SAR structure. A foreground calibration is employed to correct the offsets in the six comparators of the coarse converter, while the residual errors due to process-voltage-temperature (PVT) variations are covered by 1-bit redundancy. A background offset calibration technique based on alternate comparators is proposed, which tracks PVT variations while eliminating a dedicated calibration phase. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) can achieve 60.30dB and 68.95dBc, respectively. The power consumption of the whole system is 4.164mW under 1.1V supply voltage, thereby obtaining a figure of merit (FoM) of 9.87fJ/conv.-step.