What Can a Remote Access Hardware Trojan do to a Network-on-Chip?

Interconnection networks such as Network-on-Chips (NoCs) for multi/many-core processors are critical infrastructure of the system as they enable data communication among the processing cores, caches, memory, and other peripherals. Given the criticality of the interconnects, the system can be severely subverted if the interconnection is compromised. The threat of Hardware Trojans (HTs) penetrating complex hardware systems such as multi/many-core processors are increasing due to the increasing presence of third party players in a System-on-chip (SoC) design. Even by deploying naïve HTs, an adversary can exploit the NoC backbone of the processor and get access to communication patterns in the system. In this paper, we discuss that one or more HTs embedded in the NoC of a multi/many-core processor is capable of leaking sensitive information regarding traffic patterns to an external malicious attacker; who, in turn, can analyze the HT payload data with advanced algorithms such as machine learning to infer the applications running on the processor or reverse engineer architectural Intellectual Property (IP) of the system. Here, we entertain the idea of using routing obfuscation to achieve a desired trade-off between defense against HTs and performance penalties. We also discuss the possibility of making this trade-off a tunable design parameter that can be adjusted at run-time based on external threat perception.