Modeling and Simulation of Power-Electronic Inverters in Analog Electronic Circuit Simulators

This paper demonstrates how equivalent-circuit representations of grid-following power-electronic inverters can be realized within a SPICE-based development environment using common circuit components and VerilogA code. This facilitates computationally lean simulations of inverter networks leveraging the strengths of SPICE in large-scale simulations. We validate the approach with time-domain simulations for a modified version of the IEEE standard 118-bus system modeled in Virtuoso (a SPICE-based solver). Simulation results are compared-focusing on accuracy and computation speed-with results from a commonly used power-electronics simulation package. We note a significant decrease in simulation time with comparable signal resolution when simulating the network in SPICE.