A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET

In this paper, a 2-bit 4-level 4-wire (2B4L4W) signaling scheme is proposed, which maps two bits of information to four values distributed over four wires. The signaling scheme makes two wires transfer identical data and complementary data alternately, causing identical single-ended inter-symbol interference (ISI) at both pre- and post-cursor with an odd number cursor index. More than half the amount of total ISI is eliminated without equalizers or adaption logic. The proposed scheme doesn't incorporate the feedback loop, which allows for higher operating speed. A prototype transceiver is designed in 14nm FinFET process. The post-layout simulation results indicate that the transceiver is capable of operating at 56Gb/s over an 8.4dB-loss channel. The total power efficiency is 2.72 pJ/b.