A High Speed, Low Energy Comparator Based on Current Recycling Approach

A high speed, low energy dynamic comparator using current recycling approach is proposed in this paper. The current flowing through the preamplifier during the regenerative phase is sensed and added to the regenerative nodes for high speed operation. The increment in power is further compensated using additional clock signal to prevent the full discharge of output nodes of the preamplifier. The comparator is designed and simulated in UMC 180 nm CMOS process at 1.8 V power supply. The performance of comparator is verified at different process corners. The designed comparator operates at a frequency of 500 MHz and consumes 162 fJ of energy. The variations in latency is observed from 10 ps to 1 ns for working range of 1 V. The Monte Carlo simulations are performed for 200 samples resulting in a mean offset of-0.0056 mV and standard deviation of 7.42 mV.