An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer

This paper presents an 11-bit 500 MS/s two-step SAR ADC with non-attenuated passive residue transfer for high-speed and high-resolution operations. The proposed partial interleaved CDACs scheme in the second stage reduces the parasitic capacitance for the first stage. The comparator reusing scheme avoids the complex calibration of each offset for multi-comparators. An edge-detected calibrator is adopted to achieve low power and a constant calibrated voltage in the calibration of interstage gain error and offset. The prototype is implemented in 28 nm CMOS process. The simulation shows that the proposed ADC achieves an SNDR of 61.98 dB and an SFDR of 81.73 dB at Nyquist input at 0.9-V supply. The power consumption is 3.06 mW, showing the FoM of 5.58 fJ/con-step.