A 90 nm Static CMOS Technology Gate-Level Integrated Circuit Layout Classification and Error Detection Using EfficientNet Model

Sensitivity issues of the internal design rule check (DRC) capability of an electronic design automation tool are highlighted when the design technology used is not properly configured. However, the integration of computer vision and computational intelligence in the field of constraint engineering and integrated circuit layout has high tendency to resolve this ambiguity. In this study, vision-based architecture is integrated with deep transfer learning network to classify NOT, NAND (no fold and two-finger), and NOR logic gates with 1
$\mu \mathrm{m}$
physical gate polysilicon and 0.5
${\mu} \mathrm{m}$
gate length using 90 nm CMOS technology. Inverter designs with contact (CO) error is generated using missing CO, metal 1 in place and not fully placed, and off positioned CO via an incorporated Python-triggered tool command language (TCL) program in the Synopsys platform. EfficientNetB7 perfectly classified NOT and NAND gates, and subcategorized NOT contact error designs. Overall, the developed seamless approach in classifying gate-level integrated circuit design and predicting contact errors using EfficientNetB7 is easy to replicate and can enhance layout assessment.