Power and Thermal Modeling of In-3D-Memory Computing

In-memory computing is an efficient big-data processing method that allows for performance scalability. Although 3D-memory is an established technology to integrate in-memory computing due to the 3D-stacked logic and memory layers, there are thermal issues and power budgets that restrict the integration of this concept in a 3D-stacked memory. In this paper, we investigate the power and thermal behavior of the in-3D-memory computing device based on thermal circuit modeling. When the logic layers consume 1 W/cm
²
in each layer, the maximum power available in the logic layer is 11.4 W/cm
²
and 7.3 W/cm
²
for the 4 and 16-layer stack. For high-rise stacked memory, passive heat sinks cannot sustain the operating temperature below 85 C. In this work, the validity of the proposed simulation results is compared with a conventional simulator.