Static Timing Analysis of Sequential Circuit with GUI

The Static time analysis (STA) used to verify the timing satisfiability of the sequential digital circuit. The occurrence of data input must synchronize with the active edge of the clock else metastable error results. A dedicated tool required to analyze the timing issue; Primetime by Synopsis. The main goal of this work is to design an STA solver with open-source technology. The methodology of computation has been implemented in Tcl (tool command language) and graphical user interface (GUI) has been implemented with the toolkit (Tk) comprises of an interactive visual component. GUI provides a simple way to interact with the system and make the analysis easy to understand; while existing tool are based on hardware programming language. The user has to provide input as data and clock frequency, GUI returns the positive and negative slack up to 5-clock edges and indicate whether the metastable state error occurs or not. The presented GUI computes the slack (reserve time between and after the required time of clock and arrival time data). A binary executable file of the STA solver verifies the setup and hold timing errors.