Optimized Crosstalk Circuit for Long Wire Copper Interconnects using 45nm CMOS Inverter

Crosstalk is known as one of the main problems in chip designing. With technology scale down, interconnects have become closer to each other, and electromagnetic coupling has become a crucial factor causing system malfunction. The use of an inverter has been studied as a buffer to solve crosstalk delay problem, but it also limits its use up to some extent. In this paper, an approach to reduce crosstalk delay using π-model for an on-chip VLSI RC interconnects circuit has been presented. Also, the buffer insertion between the interconnect circuit is simulated for power and delay optimization. The complete circuit is modeled and simulated using the SPICE tool. A comparison is done between different existing models in terms of overall speed. The presented model results in a 37.4% improvement in delay with the state of the art technique.