Design and Analysis of LFSR based Content Addressable Memory

This paper presents a Linear Feedback Shift Register (LFSR) based Content Addressable Memory (CAM) that focuses on reducing the area compared to a combinational design of the memory. A simple sequential counter-based memory architecture can also be used for the same, but, an LFSR based CAM architecture increases the randomness and thus liable to acquire better access time within the memory. The design majorly consists of a Reconfigurable LFSR and an encoder module coupled with a ROM to configure the LFSR. Further, a counter is used for writing data sequentially into the memory array. The proposed architecture is simulated on Icarus Verilog to validate the hypothesis and achieved the hypothesised improvements in memory access times.