The Stability Performance Analysis of SRAM Cell Topologies in 90nm and 130nm CMOS technology

The design of highly stable Static Random-Access Memory with reliability has always been challenge giving rise to advancements in different SRAM topologies. With Scaling of CMOS technology power performance of SRAM cell topology is improved at the expense of ability to retain data which is crucial performance parameter defining reliability. The Performance of 6T (transistor), 8T, 9T, 10T SRAM cell with respect to stability with technology scaling is presented in this paper. The paper also emphasizes on the effect of variations in cell ratio and pull up ratio on the SRAM cell stability. The stability analysis has been carried out at 90nm and 130nm process node using CMOS technology in H-spice environment. The results presented in this paper shows improvement of static noise margin in read state and write state of 10T SRAM cell as compare to 6T SRAM cell by 208.7% and 23.59% respectively at 90nm process. The technology scaling resulted in the degradation of SRAM cell stability. The static noise margin in read state and write state of 10T SRAM cell is hampered by 24.11% and 10.85% respectively at 90 nm node as compare to analysis at 130nm node.