An Optimization Method for FPGA’s Logic Gates

The paper describes a method of finding optimal sets of logic gates for the development of field-programmable gate array (FPGA). The proposed method is based on the Pareto optimality search procedure. The search procedure has a number of distinctive features. At the stage of forming various combinations of technical solutions, these solutions are filtered. This filtering allows us to initially discard unnecessary sets of logic gates. Then for each combination a subset is formed. An optimal subset is found from this subset. In the set of optimal subsets, the Pareto optimality search procedure is performed. At the stage of forming a set of solutions, the proposed method takes into account the following complex characteristics: the number of transistors, the area occupied on the chip, speed, power consumption and reliability of logic gates. The developed method was programmed in the C ++ language.