The Modification of the ABC Synthesis Algorithm for FPGAs Considering Architecture Features

ABC is a tool that solves the logic optimization and technology mapping tasks in the digital circuits design flow. It is suitable for both custom and FPGA design flows. This tool is a technology independent solution and, accordingly, does not take the architectural features of the target FPGA into account. Although considering these features can significantly decrease the occupied area, in terms of programmable logic blocks and interconnections. This article presents modifications of the logic synthesis algorithms used in the ABC tool. Applying these modifications allows to obtain a more appropriate description of the circuit for performing logic architecture-oriented resynthesis.