Design and Performance Analysis of A Low Power, Low Noise 1.6GHz Charge Pump Integer-N PLL in Different PVT Corners

A fast locking low phase noise 1.6GHz PLL has been presented in this paper. The PLL was designed in 28nm technology with 1V nominal supply voltage. The phase noise of the PLL has been reduced by implementing current starved ring oscillator VCO. The lock time of the PLL is reduced by using a current steering charge pump (CP). The PLL has been designed and simulated in different PVT corners. The simulation results show that the PLL achieves lock state at only 951ns in standard typical PVT (Process, Voltage and Temperature) corner. A low phase noise of only -60.67dBc/Hz at 1MHz has been achieved. It consumes a very low area of only 50u x 45u. The layout of the circuit along with pre and post layout simulation results have been incorporated in this paper.