Design of an Analog Multi-Neuronal Spike-sequence Detector (MNSD) based on a 180nm CMOS Leaky Integrate & Fire with Latency Neuron

In this work, an analog hardware implementation of the Multi Neuronal Spike-sequence Detector (MNSD), is presented.The MNSD is a neuromorphic system for spike pattern detection based on the Leaky Integrate-and-Fire with Latency (LIFL) spiking neuron model. The LIFL neuron model is able to encode more information than simpler models like the Integrate-and- Fire thanks to the spike latency, a feature that can be exploited to tackle spatio-temporal pattern recognition tasks. The LIFL is here designed using 180nm CMOS technology, obtaining values of power consumption, area and complexity comparable to those of simpler neuron models with less biological resemblance and encoding capabilities. The LIFL is finally embedded in a spiking neural network based on the MNSD topology, and the operation of the overall system is tested for a simple character recognition task. Accuracy, precision and recall of 100% is obtained considering the one-versus-all classification scheme, for different noise levels. This confirms the validity of the overall system and acts as a proof of concept for future extension to more complex hardware recognition systems based on the MNSD