Design of A 20 - 46 GHz Balanced Broadband Power Amplifier

A 20 - 46 GHz balanced broadband power amplifier (PA) chip based on a 0.15 um GaAs pHEMT process was designed and fabricated. A balanced structure was used for power combining. Cascaded 4-stage topology was used to increase the gain of the circuit. The circuit layout was designed with a full-wave electromagnetic simulation technology, thus the electromagnetic interference inside the chip was decreased effectively．The chip was tested on wafer at continuous wave mode with the drain bias 5 V and gate bias -0.6 V respectively. The test results show that, at the frequency range of 20 to 46 GHz, the small-signal gain of the PA is higher than 20 dB and the gain flatness is lower than ±1 dB. Both the input and output return losses are below -12 dB. The 1 dB compression output power of the PA is higher than 23 dBm.