Thermal Resistance Model of Packaging for RF High Power Devices

An accurate analytic expression for thermal resistance (R
_TH
) of packaging for high power devices is presented in this paper. The interface thermal effect, sintering void and active area ratio are taken into account in this model. The model's validity is verified through 3 kinds of high electron mobility transistors (HEMTs) via comparing it with the results of numerical simulations and temperature measurements using infrared thermometry. The junction temperature (T
_j
) deviation of our model is controlled within 2°C after an amendment according to the measured data. The analytic model could estimate the device's junction temperature in early design stage based on configuration parameters and would provide a basis for the package's thermal design.