Modelling and Mathematical Optimization for Capacity Planning of a Semiconductor Wafer Test Module

This paper focuses on scheduling and capacity planning problems in semiconductor wafer test. The planning of wafer test as the final stage of the semiconductor frontend manufacturing process is very complex due to many uncertain factors. Yet the processes and system allocation are not fully automated at Infineon Technologies AG in Regensburg, but partly involved with manual handling. For this reason, a mathematical optimization program has been developed to compute a realistic delivery plan including a machine allocation plan. Various data on internal resources and dedication matrices were collected by specialized departments and serve as a basis for optimization, which was carried out with IBM OPL CPLEX Optimization studio using mixed-integer programming. The focus was on the optimization of delivery due date at the lowest possible costs in terms of setup and capacity.