FPGA Implementation of Memory-Based Digital Predistorters with High-Level Synthesis

This paper presents a scalable look-up table (LUT) architecture for implementing digital predistortion (DPD) linearizers in a field programmable gate array (FPGA) by using the high-level synthesis (HLS) software. This architecture can be used in most memory-based DPD behavioral models whose basis functions can be expressed as a combination of basic predistortion cells (BPCs). The advantages of the proposed LUT-based architecture are evidenced in terms of resources usage, throughput, and power consumption of the corresponding programmable logic (PL). The DPD linearization performance was tested considering different LUT sizes on a load-modulated balanced amplifier (LMBA), using two LTE 20 MHz signals over a total 60 MHz instantaneous bandwidth.