Industry's First Recessed Gate Transistor Technology for Sense Amplifer Circuit in DRAM: Phenomena of Randomly Threshold Voltage High Flying and Subthreshold Swing Degradation

We have fabricated a recessed gate (RG) transistor for sense amplifier (SA) in high density DRAM and have compared it with a conventional planar gate (PG) transistor in terms of VT mismatch performance. The mismatch was reduced into 22% compared to PG and it was more superior at VT mismatch gap 86% between cold-hot temperature. It was attributed to the lower channel doping and the larger effective channel length in RG than PG. But RG showed phenomenon of randomly threshold voltage high flying in a few levels of 1K array, which makes VT mismatch of some RG transistors worse. In addition, the subthreshold swing (SS) of RG is inferior to that of PG. Failure analysis and TCAD modeling showed that the random VT high flying is caused by the Fermi-Level pinning at polysilicon gate grain boundaries, its effect increases only within a specific geometric angle range between grain boundary and channel surface and SS degradation comes from an electric field spreading at recessed channel corner, resulting in relatively low surface potential at channel corner than that of channel center. The above two phenomena were technically controlled and the industry's first RG technology was applied to SA transistor for highly scaled DRAM production.