Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking

Fabrication of stacked CMOS tiers in a 3D sequential integration requires development of low thermal budget process modules. High-quality SiO
₂
interfacial layer (IL), obtained up to now only by high-temperature (≥850 °C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL's grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E' defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO
₂
defects at low temperatures (100-300 °C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO
₂
quality and reliability surpassing a 900 °C oxide.