Key Length Reconfigurable ARIA Hardware with S-box Optimization

As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16,822 gate counts. This result showed 23% area reduction compared to previous work.