Low Power Design of Various D-Flip-Flop Techniques using CNFET: A Comparative Study

Technology advancement leads to device operation at sub-threshold level and must be scaled down to nanometer range. Eventually speed and power related issues arise in logic circuits. D-Flip-Flop (DFF) is heart of the memory storage system. The work in this paper shows the basic implementation of different design techniques of D Flip Flop using Carbon Nanotube Field Effect Transistor (CNFET) as low power element. It is analyzed and compared with existing conventional CMOS technology using HSPICE simulation tool at 32 nm technology node with 1.42nm CNT (Carbon Nanotube) diameter. The power delay product (PDP) simulation is carried out. DFF based on CMOS, C2MOS (Clocked CMOS), POWER PC (Phase clock), GDI MUX (Gate Diffusion Input Multiplexer), and TSPC (True single phase clocked) using CNFET has 76.74%, 71.16%, 35.28%, 62.62% and 60% less PDP compared to CMOS logic. It clearly depicts that the DFFs designed using CNFET have better performance.