24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µm2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference

High-density embedded nonvolatile memory (eNVM) at advanced technology nodes is still in great demand for SOC chips used in consumer electronics, self-driving cars, industrial control, and IoT edge devices. Although embedded NOR Flash is still main stream, its process complexity and high integration cost make it difficult to scale beyond 28nm. RRAM has become a promising alternative owing to its excellent scalability, low power, and compatibility with logic processes [1 -6]. However, several challenges still exist that restrict RRAM from practical eNVM applications, as shown in Fig. 24.2.1. 1) a high supply voltage is needed, because of high operation voltages and a considerable voltage drop on write path. 2) The IR drop on write path varies significantly with the distance of a cell from the peripheral circuits. 3) Prior self-write termination (SWT), with its abrupt cutoff, fails to form dense conductive filaments (CFs). While delayed termination helps to alleviate this issue, its delay time is not optimized for fast and slow cells [3]. 4) Previous read reference schemes that use a small number of HRS/LRS cells may collapse when encountering tail bits, resulting in a poor reference [6]. In this work, we demonstrate a 1Mb 14nm-FinFET RRAM with a 0.022 μm
²
cell size. The cell array is in a deep N-well with adequate P-substrate biasing to alleviate the difficulty of high voltage transfer. Placing the bit line (BL) and source line (SL) drivers on the top and bottom of the array reduces the IR-drop variation for near and far cells. Self-adaptive delayed termination (SADT) adjusts the termination time according to cell characteristics (fast or slow), helping to generate robust CFs. A read reference with multiple dummy 1T1R cells avoids the reference collapse issue. The test chip supports reliable read operation at a minimum supply voltage of 0.5V from -40°C to 125°C.