10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter

A continuous-time delta-sigma modulator (CT-DSM) ADC is commonly used in audio applications because of its high energy efficiency and driving-friendly front-end compared with its discrete time counterpart. A resistive DAC (R-DAC) is widely used for its intrinsic low flicker noise. However, the design of a high PSRR and low flicker noise reference generator for R-DAC not only consumes extra power and area with an external RC filter [1] but also limits the peak SNDR performance [2]. In contrast, a current-steering DAC (I-DAC) has intrinsic PSRR. In addition, the use of a tri-level implementation with a dumped buffer reduces noise with a small input signal, which improves dynamic range (DR), but flicker noise from the bias circuit still limits the peak SNR of the ADC. Instead of using large-sized transistors or an off-chip RC filter for required low flicker noise, the sample-and-hold noise filter [3] is proposed for a low noise I-DAC by filtering the bias noise with an off-transistor-based filter, which requires periodic refreshing to compensate the bias voltage drift due to the gate-leakage current of the DAC cells. However, a trade-off between bias voltage drift and folded sampling noise of this technique limits its usage in more advanced technology because larger gate-leakage current is expected. In order to solve aforementioned problems, we introduce a CT-DSM ADC with a gate-leakage compensated off-transistor (GLCOT) based I-DAC bias noise filter without extra off-chip components which is suitable for true wireless stereo (TWS) applications. The ADC achieves 104.4dB DR and 100.6dB SNDR in 24kHz bandwidth while consuming 116 $\mu$ W. This corresponds to a Schreier FoM
DR
of 187.5dB and FoM
SNDR
of 183.7dB, respectively.