Modifying SOI Properties by the CO+ Molecular Ion Implantation

Using low-k oxide silica based dielectrics is the usual approach to diminish signal interconnections in VLSI CMOS ICs. To decrease this effect in SOI ICs, a high resistivity silicon substrate with a trap-rich (HR-TR) layer is used. We study the properties of standard SOI wafers both with high-k or silica BOX and substrate layers after the high fluence CO
⁺
implantation for using them instead of HR-TR SOI wafers.