A Low Power Sub-GHz PLL with Optimized LO Distribution Circuit

A wideband fractional-N phase-lock loop (PLL) is designed for sub-GHz wireless communications. The local oscillator (LO) distribution circuit is optimized with a low power consumption and high output amplitude to drive the mixer and power amplifier of the transceiver. Implemented with a commercial 0.13-μm CMOS process, the proposed PLL has a working range of 300MHz~l.26GHz with 3.5mW power consumption, including all the buffers from a 1.2V supply. It occupies a silicon area of 0.33mm
²
.