A 5G Millimeter Low Power Phase-Locked Loop in Low-Cost 0.18-μm CMOS

This paper presents a phase-locked loop using an LC oscillator and digital frequency divider in low-cost 0.18-μm CMOS process. The PLL fully covers the 5G millimeter-wave band, i.e., it can be locked from 24.5 to 27.25GHz. Switched capacitors array is used in voltage-controlled oscillator (VCO) to reduce the gain of VCO. A patterned ground shield inserted between the center taped symmetric inductor and silicon substrate is also included in VCO design. The frequency dividers are composed of a divider by 2 prescaler, a divider by 8 and an asynchronous 16 counter. The power consumption of whole PLL including buffers is about 43.6mW from 1.8/1.2V supplies. The chip size is 0.95 × 0.8mm
²
including all test pads.