A 56–66 GHz Quadrupler with 19.6dB Conversion Gain and 2.6dBm Output Power in 65nm CMOS

A high gain CMOS quadrupler based on the cascaded push-push doubler topology is presented in this paper. Transformer based baluns are utilized for single-to-differential transformation and impedance matching. Central capacitors are applied to weaken the impact of the leaked 2
^nd
harmonics. Effect of the bias voltage on the 2
^nd
harmonic with different input voltage swing is analyzed, and the efficiency is improved by tuning the bias. The 3dB bandwidth of the output power is about 10 GHz from 56 to 66 GHz with a maximum conversion gain of 19.6dB when the input power is -17dBm. Including the buffers, the power consumption of the entire chip is 121mW and an efficiency of 1.5% is demonstrated. This frequency quadrupler is fabricated in 65nm CMOS process and occupies 0.712mm2 silicon area.